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Need to update the Boot modules for both the M3 and 28x side of Concerto. (1) M3 -- Show the clock frequency for all 4 clock domains (M3, 28x, analog, other). The device has some restrictions -- running Arm at 75 means DSP can run at 150. Running both at 100MHz is OK. Other restrictions that we should check and enforce to make sure we don't overclock things. This is done on the M3 side. (2) M3 -- Include FLASH wait state configuration to make sure we're running FLASH with correct wait states. (3) 28x -- FLASH config similar to (2). (4) 28x -- if possible, check to make sure that the 28x frequency matches the read-only PLL registers. This would double-check that the M3 configuration correctly is lined up correctly.
For (1), this work was done in previous checkins (with SDO CQ). Both M3 and C28 frequencies are computed and held in the M3 Boot module, and viewable in XGCONF. The Analog C28 frequency is not managed by the M3 and is not shown. For (2) and (3), these were fixed under Bug 367140. Rejected (4) because of limited visibility of the PLL registers from the C28-side, and the runtime computational overhead that would be introduced for this check.
closing bugs that have been in resolved state for more than a year
in fixed state for more than one year
